This application is a continuation of co-pending U.S. application Ser. No. 11/580,064, which was filed Oct. 13, 2006, and is allowed, which is a continuation of U.S. application Ser. No. 11/037,696, which was filed on Jan. 18, 2005 and issued as U.S. Pat. No. 7,123,050, which is a divisional of U.S. application Ser. No. 10/239,133, which was filed Sep. 19, 2002 and issued as U.S. Pat. No. 6,864,711, which was a U.S. national phase of International application Number PCT/US01/01793, which was filed Jan. 20, 2001, which claims the benefit of 60/177,533 filed Jan. 21, 2000.
1. The Field of the Invention
The present invention relates generally to a programmable array logic circuit employing non-volatile ferromagnetic memory cells. More particularly, the present invention uses a non-volatile ferromagnetic memory cell to temporarily store binary data.
2. The Background Art
Programmable logic devices have any number product sets, usually in groups of four (4), eight (8), sixteen (16) or more bits, although of ten in groups often (10). The arrays are programmed for application-specific tasks to be performed within digital electronic circuits. The fusible link types cannot be re-programmed, but those employing EEPROM and Flash can. For those PALs which use fusible links, the data in the “D” registers is lost at power off. For those that use EEPROM and Flash as replacements for the “D” registers, data is not lost at power off time.
Up to the present, traditional PALs have used “D” type flip-flops for product registers. Lately, however, some fabricators have begun using EEPROM and Flash technology to replace these. These last two technologies have draw-backs, however. EEPROMs are cumbersome to re-program, both are slow to re-program, exhibit “write fatigue,” thereby limiting their useful life, and must be mass-written to re-program.